1. Field of the Invention
Embodiments of the invention relate to a semiconductor device and a method of fabricating the semiconductor device. In particular, embodiments of the invention relate to a semiconductor device comprising a device isolation layer disposed in a trench and a method of fabricating the semiconductor device.
This application claims priority to Korean Patent Application No. 10-2005-0070322, filed on Aug. 1, 2005, the subject matter of which is hereby incorporated by reference in its entirety.
2. Description of Related Art
As semiconductor devices become more highly integrated, the size of a unit cell array in an individual semiconductor device decreases, requiring a reduction in the size of device isolation layers in the unit cell array. Deep and narrow device isolation layers can be formed in a substrate when using a trench isolation process, unlike when using conventional local oxidation of silicon (LOCOS) device isolation techniques. Trench isolation processes are used widely in the fabrication of highly integrated semiconductor devices.
Trenches formed in a cell array region of a semiconductor memory device may have different depths than trenches formed in a peripheral circuit region of a semiconductor memory device. However, properly forming device isolation layers in the trenches may be more problematic when the depths of the trenches are different. In addition, when the aspect ratio of a trench is relatively great, it is more difficult to fill the inside of the trench with a device isolation layer without forming a void in the device isolation layer.
FIG. 1A is a plan view illustrating device isolation layers formed in a cell array region A and a peripheral circuit B of a conventional flash memory device. FIG. 1B is a cross-sectional view taken along a line I-I′ of FIG. 1A and illustrating device isolation layers formed using a conventional method. FIG. 1C is a cross-sectional view taken along line I-I′ of FIG. 1A and illustrating trenches in which a selective etching (i.e., pull-back) process has been performed on a silicon nitride layer.
Referring to FIGS. 1A and 1B, line-type active regions having uniform widths and uniform distances that are respectively disposed under portions of hard mask pattern 20 are formed in cell array region A of the flash memory device illustrated in FIGS. 1A and 1B. Also, device isolation layers 40a having uniform widths and uniform distances are formed in trenches having uniform depths. However, peripheral circuit region B comprises a plurality of trenches having different shapes, and the layout of device isolation layers 40b, 40c, and 40d in peripheral circuit region B (and a portion of cell array region A) is more complicated than the layout of device isolation layers 40a formed entirely in cell array region A. The aspect ratio of a selected trench in peripheral circuit region B may be larger than the aspect ratio of a selected trench in cell array region A. Additionally, some or all of the trenches disposed in peripheral circuit region B may have different widths and/or depths than one another.
Referring to FIG. 1B, when forming the trenches, a hard mask pattern 20 is formed on a semiconductor substrate 10. Hard mask pattern 20 comprises a pad oxide pattern 22 and a silicon nitride pattern 24 stacked sequentially. Trenches having various aspect ratios are then formed in semiconductor substrate 10 using hard mask pattern 20 as an etching mask. The trenches are then filled with an insulation material. Next, a chemical mechanical polishing (CMP) is performed to expose hard mask pattern 20 and form device isolation layers 40a, 40b, 40c, and 40d. 
A void 11 may be formed in a specific region of device isolation layers 40b, 40c, and 40d of peripheral region B (e.g., in a device isolation layer having a relatively large aspect ratio, or in a region where trenches cross). A void 11 may occur because all of the trenches are filled with the same insulation material without regard to the different shapes and aspect ratios of the trenches. Moreover, when an insulation material that is only useful for filling trenches formed in cell array region A is used to fill the trenches formed in peripheral circuit region B, voids 11 will unavoidably be formed in the trenches of peripheral circuit region B that have relatively large aspect ratios. Thus, difficulties arise when the trenches of cell array region A and the trenches of peripheral circuit region B are filled simultaneously.
Alternatively, a device isolation process for improving the gap-filling characteristics of the trenches formed in peripheral circuit region B may be performed. That is, a selective etching (i.e., a pull-back) process may be performed on silicon nitride layer 24 (see FIG. 1C). Referring to FIG. 1C, a hard mask pattern 20 comprising a pad oxide pattern 22 and a silicon nitride pattern 24 stacked sequentially is formed on a semiconductor substrate 10, and trenches having various aspect ratios are formed in semiconductor substrate 10 using hard mask pattern 20 as an etching mask. Then, semiconductor substrate 10 is put in a solution adapted to selectively etch silicon nitride pattern 24, which comprises a plurality of segments 25. Thus, sidewalls of segments 25 are etched. Therefore, the widths of segments 25 of hard mask pattern 20 may be reduced. Accordingly, the gap-filling characteristics of the trenches of peripheral circuit region B can be improved. However, the preceding process may unavoidably lead to variations in the width of the active region. In particular, the width of the active region is not maintained uniformly in a memory device comprising line-type active regions in cell array region A. Thus, variation of a threshold voltage in the cell transistor increases.